ASIC Engineer Intern, Design Verification

Company: Meta India (Bangalore)

Duration: 12–16 Weeks

Responsibilities

Write test content, checkers, and coverage using SystemVerilog, UVM, or C.

Debug test failures and verify fixes with design teams.

Automate verification workflows using Python or Perl scripts.

Analyze and improve design architecture and microarchitecture.

Requirements

Education: Pursuing a BS/MS/PhD in Electrical or Computer Engineering (must return to program post-internship).

Core Knowledge: Computer Architecture and Logic Design fundamentals.

Languages: SystemVerilog, VHDL, Verilog, C, Python, or Perl.

Work Auth: Must have authorization to work in India.